Graduated students: Jude Rivers, Ed Tam, Viji Srinivasan, Hsien-Hsin Lee, Mike Geiger and Paul West
Current students: Yue Li

This project start early in my career at Michigan with numerous studies on instruction cache organization, data cache organization and prefetching. These cache designs targetted both high-performance and low power systems. Much of this work evaluates different "multi-lateral" L1 cache organizations. Multi-lateral caches partition a reference stream into multiple, disjoint, reference streams which have different access characteristics. We can then develop custom cache designs that exploit the individual characteristics of each substream to improve overall cache performance.

Partitioning cache structures has traditionally been restricted to levels in a cache hierarchy and to separating instruction from data in the first level of the hierarchy. There have been studies examining data cache partitioning strategies, but few of these have made it into current processors. Data cache partitioning appears to be the most likely design approach to address the future requirements of memory subsystems. Careful partitioning of the data reference stream enables multiple heterogeneous caches to provide improved performance, both latency reduction and reduced power consumption, over a unified data cache approach. Some open research questions are:

• How can the reference stream be partitioned?
• What is the best cache organization for each partition?
• Are these cache designs language independent?
• What are the best code layout heuristics during compilation?

To answer these questions, we are expanding our prior research in region based caching to study alternate programming methodologies, including new languages and compilation techniques. We are also exploring how different address regions can be managed in a parallel multicore processor environment; this research include both new cache designs to support data flow patterns between processors on a multicore chip as well as new active memory management techniques to monitor and reconfigure memory resources on multicore designs.

Graduated students: Allen Cheng, Steve Hines, Mark Searles and Chris Zimmer
Current students: Yuval Peress

coming soon (FITS, IRF, LDRF, register queues, branch prediction)

Current students: Daniel Chang

We are in the early developmental state of a new project to use a combination of hardware and software techniques to reduce the vulnerability of computer systems and applications to virus attachs. The idea is to create many different copies of an application that are designed to frustrate malware attack while maintaining the ability to manage a large application base as if it were undifferentiated.

We will provide more detail when the project is more mature - that is when we have funding or published results.