08:50 - 09:00 Opening remarks
09:00 - 10:00 Keynote: Youfeng Wu (Intel)
Could HW/SW co-designed in-order cores compete with out-of-order cores?
10:00 - 10:30 Break
10:30 - 12:00 Processors
Abhishek Deb*, Josep M. Codina, Antonio Gonzalez (*Universitat Politecnica de Catalunya, Intel Research Labs Barcelona_
The Good Block: Hardware/Software Design for Composable, Block-Atomic Processors
Bertrand A. Maher*, Katherine E. Coons, Kathryn S. McKinley, Doug Burger** (*Intel, University of Texas at Austin, **Microsoft Research)
Improving Low Power Processor Efficiency with Static Pipelining
Ian Finlayson, Gang-Ryung Uh*, David Whalley, Gary Tyson (Florida State University, *Boise State University)
12:00 - 13:00 Lunch
13:00 - 15:00 Parallelization
A Constraint Programming Approach for Instruction Assignment
Mirza Beg, Peter van Beek (University of Waterloo)
On-line Trace Based Automatic Parallelization of Java Programs on Multicore Platforms
Yu Sun, Wei Zhang (Virginia Commonwealth University)
MATLAB Parallelization through Scalarization
Chun-Yu Shei, Adarsh Yoga, Madhav Ramesh, Arun Chauhan (Indiana University)
JIT Compilation Policy on Single-Core and Multi-core Machines
Prasad A. Kulkarni, Jay Fuller (University of Kansas)
15:00 - 15:30 Break
15:30 - 17:00 Potpourri
Characterizing the Performance and Energy Efficiency of Lock-Free Data Structures
Nicholas Hunt, Paramjit Singh Sandhu, Luis Ceze (University of Washington)
Implications of Program Phase Behavior on Timing Analysis
Archana Ravindar, Y. N. Srikant (Indian Institute of Science)
Aggressive Function Splitting for Partial Inlining
Jun-Pyo Lee, Jae-Jin Kim, Soo-Mook Moon (Seoul National University)