PPT Slide
Cost Evaluation of VM
- To run with a 10% slowdown would require that the program achieve one page fault per one million memory accesses!
- Luckily, as mentioned with TLB cache hits, program exhibit spatial and temporal locality.
- The next instruction or data reference is usually close to the current instruction in memory and close in future execution.
- The result is that a program doesn’t usually demand that all of it’s logical pages be assigned to physical pages. Book: for typical programs, 25% to 50% of mapped pages result in acceptable low page fault rates.