DRAM Examples
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Assume the following:
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1 clock cycle to send the address
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15 clock cycles for each DRAM access initiated
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1 clock cycle to send a word of data
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cache block of four words
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Miss penalty for a one-word-wide bank of DRAMs:
1+4*15+4*1 = 65 clock cycles
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Miss penalty for a two-word-wide bank of DRAMs:
1+2*15+2*1 = 33 clock cycles
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Miss penalty for a four-word-wide bank of DRAMs:
1+1*15+1*1 = 17 clock cycles
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Miss penalty for an interleaved memory with 4 banks of DRAMs:
1+1*15+4*1 = 20 clock cycles
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