Cache Impact on Performance
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Consider only the impact of an instruction cache.
Assume the following:
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miss penalty is 10 cycles
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miss ratio is 0.10
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The number of cycles disregarding pipeline and data cache stalls
would be:
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inst_cnt*(hit_time+miss_rate*miss_penalty)
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inst_cnt*(1+0.10*10)
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inst_cnt*2.0
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With a miss ratio of 0.05, the number of cycles would be:
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inst_cnt*(1+0.05*10)
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inst_cnt*1.5
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